module top_module (
    input clk,
    input reset,
    output OneHertz,
    output [2:0] c_enable
); //

    wire	[3:0]	Q0;
    wire	[3:0]	Q1;
    wire	[3:0]	Q2;
    /*
    always @(posedge clk) begin
        if(reset) begin
            c_enable[0] <= 1'b0; 
        end
        else begin
            c_enable[0] <= 1'b1;
        end
    end
    */
    
    assign c_enable[0] = ~reset;
    assign c_enable[1] = (Q0 == 4'd9) && c_enable[0];
    assign c_enable[2] = (Q1 == 4'd9) && c_enable[1];
    assign OneHertz = (Q0 == 4'd9) && (Q1 == 4'd9) && (Q2 == 4'd9);
    //assign OneHertz = (Q2 == 4'd9) && (Q1 == 4'd9);
    
    bcdcount u_bcdcount_0(
        .clk(clk),
        .reset(reset),
        .enable(c_enable[0]),
        .Q(Q0)
    );
    
    bcdcount u_bcdcount_1(
        .clk(clk),
        .reset(reset),
        .enable(c_enable[1]),
        .Q(Q1)
    );
    
    bcdcount u_bcdcount_2(
        .clk(clk),
        .reset(reset),
        .enable(c_enable[2]),
        .Q(Q2)
    );

endmodule
